It is well known that some memory devices, such as a memory controller, must support two sources of cycle requests and often receive identical address requests within the same memory cycle and it is not uncommon for the requests to conflict. When this occurs, the requests cause the set up times of the synchronous device to be violated, resulting in metastability. When metastability occurs, an analog signal is latched into the device causing oscillation of the output until the state is resolved. For example, a memory controller is required to periodically access and maintain the data stored in memory. The controller receives two types of memory requests: access requests and refresh requests and occasionally, both the access request and the refresh request, address the same memory location during the same memory cycle. Since the device is unable to resolve the identical address requests within the same memory cycle, metastability in the device results.
Arbiters are well known in the art as a means for resolving identical address requests within the same memory cycle, and hence, a means for eliminating metastability. Typically, an arbiter circuit is comprised of cross-coupled NAND gates or a flip-flop, commonly referred to as a latch. However, using a single latch permits the metastable condition to propagate into the memory control circuit. In addition, the arbiter circuit unnecessarily delays both requests by the same amount of time.
The present invention is directed toward overcoming each of the deficiencies mentioned above.